High fidelity audio amplification using linear amplification suffers from poor efficiency, excess heating and reduced reliability of power electronic components, and the need for heavy and bulky heat sinking. In portable applications, poor efficiency also leads to shorter and generally unacceptable battery life.
High fidelity linear amplification using class-A amplifiers offers the least distortion but requires its power transistors to continuously carry current and dissipate power. Class B amplifiers introduces a dead-band in the circuit operation where neither transistor conducts but at the expense of increased distortion. Class-AB amplifiers attempt a compromise, but still sacrifice audio quality for efficiency and current consumption.
With the advent of power MOSFETs, a new type of audio amplification with higher efficiency became possible using class-D amplification methods. Class-D amplifiers operate by driving the speaker digitally using a push-pull power output stage or H bridge comprising continuously switched power MOSFETs. By driving a speaker on and off digitally at high frequencies, generally above the audible range, and through control of the pull-up and pull-down times using pulse width modulation (PWM) techniques, the speaker can be made only to respond to the audio content encoded in the PWM modulation.
The switching noise is naturally filtered by the inertial mass of the speaker's voice coil, unable to react to higher frequencies. Further filtering can also be performed digitally in the signal processing and decoding scheme, and additionally through a passive LC network as needed. Additional digital signal processing requires increased computing and more power consumption in digital circuitry. This extra power loss in part offsets the benefits of increased power efficiency of class D audio power amplification, especially at lower output power levels.
Ignoring signal processing related power consumption, the power efficiency of a class D power amplifier relies on using low-resistance power MOSFETs, typically four per speaker, i.e. for each “channel”. Cost, on the other hand, depends on using the smallest power MOSFETs implemented in the lowest cost process to minimize the cost per MOSFET switch. For a given MOSFET, a smaller area decreases cost at the expense of increased on-resistance. Larger die have lower on-resistance and improved power efficiency, but higher cost. This area and cost versus power efficiency tradeoff for any power MOSFET is expressed as the product of on-resistance RDS(on) and the die area A, so that a MOSFET constructed with a given technology and specific-on-resistance RDSA and of a given size A1 will have an on-resistance R1 given by
      R    1    =                    R        DS            ⁢      A              A      1      
The power output stage may comprise monolithically integrated power MOSFETs or separately-packaged discrete power MOSFETs. Monolithic solutions are desirable for integrating drive electronic circuitry with the power devices themselves, but require much larger die sizes because the on-resistance of lateral devices are typically much higher than vertical discrete devices, especially for devices with blocking voltages over 12 volts. This is because the area efficiency of lateral devices is at best, no better than half that of vertical devices since a lateral device devotes valuable silicon real estate to both drain and source contacts. In contrast, a vertical power MOSFET uses almost the entire top-side as its source connection and 100% of its backside as its drain connection. The RDSA area efficiency and specific on-resistance of vertical devices can be one-fifth and even one-tenth that of a comparable breakdown lateral device.
Trench & Planar Vertical DMOS:
One such vertical prior art device, an N-channel vertical trench-gate DMOS power MOSFET 1 is illustrated in FIG. 1A. The device comprises an array of active gates embedded in trenches 4 etched into the silicon where the trenches are lined with a thin gate oxide 9 and then filled with conductive polysilicon 10 to form the gate electrode of the MOSFET device. The trench gates 4 are formed in an epitaxially deposited layer 3, shown as N conductivity type material grown atop an N+ heavily doped substrate 2. The trench gates are contacted by a special gate 14 where the polysilicon 15 exits the trench and is contacted by metal 16, separately from source connected metal 13.
Between adjacent trench gates, P-type body regions PB are implanted and optionally diffused to form the body or channel region 5 of the MOSFET. Heavily doped P+ region 6 is used to make Ohmic contact to P-body region 5. Inside said PB body regions, N+ source regions 7 are masked and implanted abutting the trench gates 4, forming the N-channel MOSFET's heavily-doped source regions. The device is called DMOS because the device has two junctions one inside the other, i.e. where body 5 is formed and contained within drain epitaxy 3 and source 7 is formed and contained with body 5, hence the acronym D for “double”. The term DMOS originally stood for a MOSFET with a double diffused source-channel, but new fabrication methods have emerged for forming the double junctions with minimal or no high temperature diffusions.
Top source metal 13, typically comprising aluminum, aluminum silicon, or aluminum-copper-silicon is used to contact both N+ source regions 7 and P+ regions 6, and short them together. Aside from top metal 13, a barrier metal, typically a refractory metal such as titanium, platinum or tungsten is preferably employed to prevent metal alloying from spiking through the junction and shorting out the device. Conduction is vertical, with a positive potential applied via metal 16 onto poly gates 15 and 10, an N type inversion layer is induced in PB body regions 5 along the side of trenches 4, allowing current to flow from positively biased N+ drain 2, through epitaxial layer 3, into said channel, through N+ region, and out grounded source metal 13. Ohmic contact is made to the backside of N+ substrate 2 using gold or titanium-nickel-silver sandwich metal after substrate 2 is mechanically thinned and etched to provide good Ohmic contact and contribute a reduced magnitude of substrate resistance.
Ohmic contact to the top-side source and body regions is also critical to achieve reliable device operation. A source-body-short is important to bias the body at the source potential to eliminate any body-effect induced threshold shifts, and to prevent parasitic NPN bipolar transistor conduction. The parasitic NPN bipolar transistor comprising N+ 7 as the parasitic emitter, PB body 5 as the bipolar's base and N− epitaxy 3 as the collector is in parallel with the vertical MOSFET. So long that the emitter-base regions remains shorted during current transients the bipolar remains off and its collector-to-emitter breakdown is equal to the device's BVCES, the same as the MOSFET's BVDSS. If substantial voltage drop occurs in the silicon so that VB>VE despite the emitter-to-base surface short, then the N+ region will begin to inject electrons and the bipolar will snapback to a lower breakdown which will likely destroy the device.
An optional deep P+ region dP+ layer 8 may be included in every cell, in a few of the cells, or along the device's periphery and under than gate pad and gate bus regions. If region 8 is doped more heavily than PB body region 5 and is slightly deeper, then avalanche breakdown will occur first in N− epitaxy layer 3 under dP+ diodes 8 and not in the active cells. By avoiding avalanche in the active cells and in PB body regions 5, the likelihood of device snapback from parasitic NPN conduction is greatly reduced. The device is therefore made avalanche rugged.
The on-resistance is made low by integrating a plurality of active trench gated cells at a high density, by doping N−epitaxy layer 3 to the highest possible concentration to meet the requisite breakdown voltage of the device, and by keeping the channel length, the distance between the bottom of N+ 7 and PB 5, as short as possible without inducing punch-through breakdown. In a device with no deep region 8 in the active cells, the higher the active cell density, the lower the RDSA of the device.
Trench power MOSFETs have become an industry standard device since the early 1990's and are well known in the prior art. A description of a prior art trench DMOS fabrication methods is discussed in U.S. Pat. No. 6,413,822 “A Super-Self-Aligned Trench-Gate DMOS with Reduced On-Resistance” as an example.
Trench power-MOSFETs are manufactured and commercially available in complementary processes. Device 1 of FIG. 1A as shown comprises an N-channel MOSFET while cross section 20 of FIG. 1B illustrates a P-channel trench-gated DMOS transistor. The device parallels the N-channel except that P-conductivity type material is substituted for N-type and vise versa. P-channel fabrication starts with P+ substrate 21 and P-type epitaxial layer 22 with NB body region 24, N+ region 25, P+ source 26, active trench gates 23 with gate oxide 27 and conductive polysilicon embedded gates 28, and gate contact polysilicon 33 in non-active trench 32. Top-side contact is facilitated through gate metal 34 and source metal 31 with barrier metal 30.
Generally the same barrier metal is used for fabricating both N-channel and P-channel trench devices. The doping of polysilicon gate material 28 in device 20 may be either P-type or N-type depending on threshold voltage considerations, but in general P-type polysilicon is preferred for making P-channel devices, and N-type polysilicon is preferred for N-channel devices. Mask sets and cell geometries are interchangeable, meaning the same mask set can be used to make both N-channel and P-channel trench DMOS transistors, generally in only 4 to six masking steps. Wafer fabrication is much simpler and lower cost than CMOS wafer fabrication. Whether P-channel or N-channel DMOS, the drain contact to such vertical devices is made on the wafer's back-side.
A less efficient predecessor to the trench DMOS device is the vertical planar DMOS. Dating back to the late 1970's, the planar DMOS has its channel located along the silicon surface rather than on the side of a vertical trench. N-channel planar DMOS 40 in FIG. 1C illustrates PB body region 43 extends laterally under gate polysilicon 47. N+ source 45 also extends under polysilicon gate 47 but to a lesser extent. The difference in the two junction depths forms the DMOS channel region, where current flows laterally before turning perpendicular to the wafer's surface and flowing vertically into epitaxial layer 42 and out the backside of N+ substrate 41.
Polysilicon gate 47 formed atop gate oxide 46 is typically used as a mask to implant the body region 43. The body is then diffused at a high temperature for twelve to twenty hours to diffuse laterally along the surface and vertically into the epitaxial layer. The N+ source 45 requires little subsequent diffusion to complete the channel structure.
Unlike the trench DMOS devices of FIGS. 1A and 1B, the vertical planar DMOS of FIG. 1C relies on high-temperature diffusion and long times to drive the body region 43 under the gate to form the device's channel region. If the PB region 43 is too shallow the DMOS will exhibit soft I-V characteristics of a device in punch-through breakdown. If on the other hand the depth body 43 is too deep, it will pinch the current flowing in the epitaxial region under gate 47 between adjacent body regions 43. This pinch resistance causes the device's on-resistance to increase and places a very practical limit on the maximum cell density and minimum specific on-resistance achievable using planar DMOS fabrication and structures.
The body diffusion can be replaced with a high energy tilt implant at 45 degrees, thereby implanting dopant at an angle to reach laterally beyond the edge of polysilicon gate 47. The wafers must be rotated during the tilt implant to maintain a directionally uniform penetration beneath the polysilicon gates. The cell density of the planar DMOS structure remains limited since a deeper body region 43, regardless how it's formed, has a risk of causing the unwanted pinching effect and offsetting the lower channel resistance with a greater pinch resistance.
Even so, the vertical planar DMOS can achieve specific on-resistances substantially lower than integrated lateral MOSFETs. Like the trench DMOS, it is a vertical device utilizing backside wafer contact for Ohmic connection to the drain.
For completeness, device 60 of FIG. 1D illustrates a P-channel planar DMOS transistor comprising a P+ substrate 61 with P−epitaxial drain region 62, NB body region 63, P+ source 65, P+ contact implant 65, polysilicon gate 67 with gate oxide 66 and interlayer dielectric 69 and top side metal 68. No barrier metal is generally needed since the junctions in the legacy DMOS process are necessarily deeper than used in trench DMOS fabrication.
DMOS Equivalent Electrical Network:
The electrical network of vertical DMOS, whether trench or planar in construction, involves a large number of transistors each of high resistance, connected in a massively paralleled arrangement up to million or even tens of millions of cells, all connected with a common gate, a common source and a common drain. One simplified model of a vertical DMOS power transistor is shown in schematic 80 of FIG. 2A, where devices 81A, 81B, 81C, 81D and more are connected in parallel with a single source connection, a single drain connection, and a single gate connection. By applying a gate voltage above the MOSFET's threshold, the bias turns all the MOSFET's cells “on” in parallel. Parallel conduction through millions of cells results in a low specific on-resistance for the overall device. The total resistance is the resistance of any one cell divided by the number of cells n. A composite on-resistance as low as 4 milliohms have been produced for a single device, even at 30V or greater.
A slightly more detailed equivalent schematic 90 in FIG. 2B illustrates that each device comprises an active channel MOSFET 91 with its associated channel resistance, series drain resistance 94 primarily comprising epitaxial and substrate resistance, source resistance 93 primarily involving top metal and bonding wire resistance, and gate resistance 92 comprising metal and polysilicon gate bus resistance. The magnitude and importance of each resistive component depend on where the particular cell of the transistor is located within the overall DMOS layout, and on the location and number of bond wires used to connect it.
Provided the device is not switched into the megahertz range, the gate resistance 92 can largely be ignored and the source-drain series resistance be lumped into a single resistance term called drain resistance. The resulting equivalent circuit is shown in schematic 100 of FIG. 2C where a vertical N-channel power DMOS is illustrated by MOSFET 101 and series drain resistance 102. Body-to-drain diode 103 is included in the circuit in case the polarity ever reverses across the drain-to-source, causing P-N diode conduction.
While vertical power MOSFETs, either vertical planar DMOS or vertical trench gated DMOS have many performance advantages over lateral devices used in integrated circuits, one of their major disadvantages is their inability to integrated multiple independent devices. This limitation stems from the fact that all these devices share a common drain with other MOSFETS in the die. This issue is illustrated in schematic 120 of FIG. 2D where two vertical DMOS are monolithically integrated into one die. As such MOSFETs 121 and 123 have separate gate contacts G1 and G2, separate source connections S1 and S2, separate drain-to-body diodes 122 and 124, and even separate drain epitaxial resistances 125 and 126. They, however, necessarily share a common substrate and backside drain contact “D”. This limitation is a much bigger issue than initially obvious. It limits the utility of vertical DMOS as a device, especially in its application in class D audio amplification.
Class D Audio Speaker Drivers:
The output stage for a class D audio output is typically a set of power MOSFETs configured in an “H-bridge” circuit topology. The speaker driver typically comprises two push-pull complementary half bridges with outputs A and B driven out of phase per speaker.
A complementary half bridge comprises a P-channel power MOSFET with its source tied to the positive supply rail and an N-channel power MOSFET with a grounded source sharing a common drain as its output. As shown in schematic 140 of FIG. 3A, for example high-side P-channel 141 and low-side N-channel 142 form a push-pull or complementary half-bridge with output A. A second complementary half-bridge with output B comprises P-channel 143 and N-channel 144.
Each half-bridge can in theory deliver an output voltage that switches between Vcc and ground, for a total voltage swing ΔVout equal to a full Vcc. By suspending an electrical load, in this case speaker 145, between nodes A and B of two half-bridges and by driving the two half-bridges out of phase, the voltage polarity across the speaker can reverse from +Vcc on node A and ground on node B, to a case where node A is biased to ground and node B is biased at Vcc, representing a total voltage swing ΔVout equal to a full 2·Vcc, double that of the half bridge's drive capability. So for the same supply voltage and load current, an H bridge can deliver twice the output power of a half-bridge.
The advantage of using a P-channel MOSFET such as 141 or 143 as a high-side connected switch is that they are easy to drive. Biasing the gate to Vcc, its source potential, turns the device off. Biasing a P-channel MOSFET's gate to ground or any voltage more negative than one threshold voltage Vtp below its source potential Vcc, i.e. whenever VGP<(Vcc−Vtp), turns the P-channel “on” and into a conducting state. The gate driver buffer must be designed to limit the maximum gate-to-source voltage to a potential less than the gate oxide rupture voltage VGS(max).
Because P-channel MOSFETs have a specific on-resistance at least twice that of an N-channel with comparable voltage ratings, another popular alternative to the complementary H-bridge is one comprising the two N-channel totem pole half-bridge outputs as shown in circuit 160 in FIG. 3B. A totem pole half-bridge employs two N-channel MOSFETs stacked atop one another where the output of the high-side MOSFET comprises the source of one N-channel device, while the output of the low-side device is the drain of another N-channel device. Using a source-follower high-side device such as MOSFET 161 or 163 and common-source low-side transistor such as MOSFET 162 and 164, this configuration is referred to as a totem-pole output. The term “totem pole” is a metaphor for the electrical connections or circuit topology of the high-side and low-side MOSFETs as a head-to-toe stacking of carved wood statues in ancient North America. The load, in this case speaker 165, is connected between half-bridge outputs A and B.
Like in the complementary H-bridge or half-bridge, an N-channel H-bridge comprising two half-bridge totem-pole outputs are driven out of phase to maximize the power delivered speaker 165. Unlike in driving low-side N-channel MOSFETs 162 and 164, however, high-side devices 161 and 163 are difficult to drive and must employ special floating gate drive circuits to operate properly from rail-to-rail, including driving their gates to voltages higher than Vcc, the most positive voltage in the system.
Limitations in Class-D Audio Output Stage Implementation
In Class D switching amplifiers, each H-bridge drives a single speaker, so that four power MOSFETs are needed per each speaker output. Accordingly stereo requires 8 power devices, and five-channel surround sound systems need over 20 power MOSFETs, excluding the subwoofer driver.
Aside from fully integrated versions suffering a huge area penalty, class D power amplifier implementations using discrete devices require too many components. Moreover, no package exists to efficiently co-package the large number of discrete power device die and reduce the number of discrete components requiring mounting on a printed circuit board (PCB). Such a package should low thermal resistance, exhibit minimal resistance contributions from bonding and interconnection, and maintain uniform efficiency and drive capability among its audio channels.
Moreover, what is really needed is any design, architecture or circuit technique that enables the number of packaged die to be reduced, ideally down to two or three pieces of silicon, and still employ vertical power MOSFET technology with low specific on-resistance and simple fabrication techniques. Only then can class D audio amplification be achieved in an efficient and cost effective manner, especially at higher voltages and power outputs.